In data systems used with computers the data is recorded in digital form and a clocking signal is utilized to synchronize the record and playback process. On playback the clocking signal of a frequency corresponding to the data must be generated once again. This clocking signal is used to sequence the data processing.
In the usual data recording system there is recorded a series of signals at the beginning of a data location called a preamble. The purpose for the preamble is to enable a clocking circuit to synchronize in phase and frequency with the recorded data. Such synchronization however must continue during the actual data readback operation of the system because the frequency of the data can change. Reasons for such change can involve such factors as a change in velocity of the recording media such as a rotating disc and others.
In past systems the synchronization of data and clocking signal has been accomplished by use of a phase and frequency detector to which is fed the data signal being read back and the clocking signal from an oscillator. Thus clocking pulses are received continuously and each time a data pulse is encountered it is compared with the next adjacent clocking pulse for the generation of an error signal for readjustment of the phase and frequency of the clocking signal generator. The clocking signal generator is usually a voltage controlled oscillator adjustable in phase and frequency in response to an error signal.
Since the phase and frequency detector in past systems has received the data signal and all clocking pulses from the oscillator, care must be taken to assure that the data pulses are compared with the correct clocking pulse in timed sequence. For instance if the data signal is compared with the next adjacent clocking pulse erroneously, an incorrect error signal will be generated which in turn will incorrectly adjust the phase and/or frequency of the oscillator.
Noise in the data signal, pulse crowding and other factors can result in data pulse shifting. Thus to assure that the clocking pulse is compared only with the correctly correlated data pulse, the time domain, i.e. that time period or window during which the data pulse must occur, must be small. Otherwise pulse shifting can result in the data pulse occurring within the time domain of the next adjacent clocking pulse. However this reduction of the time domain also reduces the capability of the phase lock system to recover phase and frequency locking with the data signal.
In advanced run bounded self-clocking coding systems, the recorded pulses can be further apart at times and still be interpreted as data. Thus there is greater opportunity to broaden the time domain of the phase and frequency detector. However in presently used systems, this opportunity is not utilized.
Also for purposes of fast recovery or synchronization of the phase and frequency, it is desirable that the feedback loop be of a wide bandwidth. Thus a larger error signal is generated for a discrepancy in phase or frequency between the data and the clocking signal thereby permitting adjustment at a faster rate. However the wider bandwidth also makes the system more susceptible to noise and other momentary disruptions in the data signal. In addition the clocking signal will frequently be a frequency which is a harmonic of the frequency of the data bits thereby requiring that the phase and frequency detector be of the harmonic type. With the wide bandwidth harmonic frequency and phase detector, there always exists the possibility that the phase lock loop will lock onto an improper harmonic of the actual data frequency.
Thus one approach in the past has been to utilize a two mode phase detector operable in a nonharmonic mode during the preamble phase of operation and in a harmonic mode during data readback to accommodate missing bits, et cetera. However during data readback such an operation necessitates a narrow bandwidth phase lock loop to lessen the possibility that the system will once again synchronize to an erroneous phase or frequency even though such operation slows the recovery time for the system.
It is the purpose of the present invention to provide an improved phase lock oscillator system for generating a clocking signal in a data recording system or in communications systems.